FIG. 1A illustrates a schematic view of a circuit unit of a conventional power management integrated circuit. Referring to FIG. 1A, the circuit unit includes a P-type metal-oxide-semiconductor (PMOS) transistor array 11 and an N-type metal-oxide-semiconductor (NMOS) transistor array 12. In order to reduce an area of the circuit unit and a turn-on-resistance of a source/drain region, another NMOS transistor array 13 is usually used to replace the PMOS transistor array 11, as shown in FIG. 1B. Each of the NMOS transistor array 12 and the NMOS transistor array 13 is comprised of a number of lateral diffused metal-oxide-semiconductor (LDMOS) transistors. Thus, a P-type body 131 of the NMOS transistor array 13 will work in a condition of high voltage. As a result, a punch-through leakage current is easy to be generated in the circuit unit.
Therefore, what is needed is a manufacturing method of an anti punch-through leakage current MOS transistor to overcome the above disadvantages.